GT synt

George Toms synthesis

Combinational Logic Synthesis, aimed at achieving near-optimal results aligned with designer specifications and surpassing manually aided designs in competitiveness, has been a well-known challenge for over 70 years.

The initial stride towards the automation of logic minimization took place with the introduction of the Quine–McCluskey algorithm, a milestone that could be implemented on computers. This exact minimization technique introduced the concepts of prime implicants and minimum cost covers, forming the foundation for two-level minimization.

Revolutionary Logic Synthesis Technology

Developed by GT Synthesis, LLC, the George Toms synthesis (GTs) technology represents a groundbreaking leap forward in combinational digital logic design. GTs surpasses all existing logic synthesis technologies in both quality and performance of delivered results.

Traditional logic synthesis workflows generally include the following steps:

RTL conversion to truth tables or Boolean functions
Technology-independent optimization to simplify logic
Mapping to a specific technology’s standard cells (gates)
Post-mapping optimization to meet design constraints
Test logic insertion for design-for-testability features

In contrast, GTs introduces a radically different approach built around its core innovation—the GT decomposition method.

GT Decomposition: The Core Innovation

The GT decomposition method outperforms all known decomposition techniques, including the well-established Ashenhurst-Curtis (Roth-Karp) decomposition.

GTs enables direct generation of a final gate-level netlist in a single synthesis step.

By intelligently applying different parameters and constraints in varying orders, GT decomposition dynamically adapts circuit synthesis to meet specific design goals.

GTs outperforms existing synthesis technologies across a broad range of critical parameters, including:

Performance (delay)
Power consumption
Total silicon area
Gate count
Total wire count
Input-connected wire count
Total number of gate inputs
Maximum gate output fan-out
Maximum gate level

GTs supports all standard logic gates—AND, OR, NAND, NOR, XOR, XNOR, AOI — as well as LUT-6 (look-up tables), enabling limitless design flexibility.

The result: GTs empowers designers to create thousands of optimized circuit variations for any truth table, offering unprecedented control and precision in digital logic synthesis.

Additional Capabilities

Integrated Testability – GTs can generate testable circuits directly during synthesis, eliminating the need for a separate test logic insertion stage.
Automated Test Pattern Generation – Test vectors can be created automatically alongside circuit design, simplifying verification and accelerating validation cycles.
Unified Testing Architecture – GTs introduces design adjustments that enable circuits to be tested using predefined input sets, dramatically reducing overall test complexity. This approach allows a single testing component to verify multiple subcircuits within a chip, improving efficiency and minimizing hardware redundancy.

In the Proof of concept section, you'll find a comparison of our technology's results with Gate-Level Netlists and FPGA created by leading professionals worldwide:

These results demonstrate GTs’ ability to optimize multiple interconnected parameters simultaneously, outperforming even the top global benchmark implementations.

Tools, Visualization, and Security

Beyond synthesis, GTs delivers an advanced suite of visualization, simulation, and race analysis tools—setting a new standard for gate-level design.

Remarkably, GTs runs seamlessly on standard computers, laptops, or tablets within any web browser, providing engineers with a fully interactive environment for:

Truth table manipulation
Gate library exploration
Parameters settings
Thousands of results evaluations
Gate-level netlist visualization
Logic simulation and timing analysis
Ready-to-go netlist generation
Race analysis

All synthesis data—including truth tables, gate libraries, constraints, and results—can be stored locally, ensuring maximum data security.

It is better to try something once than to hear about it a thousand times.
Please try...

1. Enter the Project name, input and output names, and conveniently paste the truth table input and output vectors. Customize synthesis options as needed:

2. Validate the Truth Table by selecting the "Show Truth Table" button:

3. Initiate the design process and generate 910 Gate-Level Netlists with a simple click on the "Start Design" button.:

4. Easily identify and display the desired Gate-Level Netlist from the Result Table by selecting (highlighting) it and clicking the "Show Netlist" button:

5. Review, modify, and simulate the schematic of the chosen netlist using the "Show Schematic" button. Optionally, save this schematic by clicking "Export Schematic":

6. Investigate potential race conditions in the selected netlist by clicking the "Show Racing" button:

7. Obtain the chosen netlist in Verilog and VHDL formats effortlessly with the click of the "Export to Verilog and VHDL" button:

This user-friendly process ensures a seamless and efficient experience in designing and working with Gate-Level Netlists

Proof of Concept

Please review GT synthesis circuit examples:

When Will It Be Available?

GT synthesis is fully implemented, debugged, and being tested on a variety of circuits.

It is easy to use:

Compatible and interoperable with all standard browsers (e.g. Chrome, Firefox, Edge, Safari, Opera, Vivaldi, Internet, etc.)
Requires no additional client-side software or plug-ins

For Details and License please contact:
Phone: USA: +1 (858) 699-8940
E-mail: n@gtsynt.com

In most cases, we can solve your problems promptly and efficiently.