GT PDBF Logic Synthesis Benchmark Suite

Purpose of the benchmark suite

This page provides reproducible PDBF synthesis problems in standard PLA format. The benchmarks include semantic control and policy functions as well as dedicated input-scalability experiments extending to one million primary inputs.

GT synthesis results are reported as simple two-input logic-gate count, maximum logic depth, and synthesis time. The present benchmark release provides the original PLA specifications and synthesis statistics. GT synthesized netlists are not included in this release.

Contextual PDBF benchmarks

These examples illustrate contextual PDBFs, as discussed in Paper II. Each benchmark represents the PDBF of block A0 (adder) in an A×B multiplier implemented using the Vedic algorithm. The admissible input combinations of A0 are determined by the outputs of the multiplier blocks that feed the adder, thereby providing the context that defines the PDBF. The table reports PLA dimensions and cube counts together with available ABC and GT synthesis results.

Where multiple synthesis results are available for the same contextual PDBF, additional lines show the corresponding ABC or GT netlist variants.

AI-Inspired Contextual PDBF Benchmarks

These benchmarks are synthetic, reproducible AI-like decision and classification functions expressed directly as contextual PDBFs. They are intended to study combinational synthesis over strongly constrained quantized feature domains; they are not results extracted from trained neural-network models and should not be interpreted as AI-accuracy benchmarks.

The current table reports 28 evaluated examples for which both GT and ABC synthesis data are available. Input features are quantized and encoded so that only the listed care terms are admissible; all other nominal Boolean input combinations are contextual don't-cares. Results are reported as Gates|Levels. Multiple GT entries show alternative synthesized implementations and therefore expose gate/depth tradeoffs rather than a single selected operating point.

Care density is |C|/2^PI. Where several GT implementations are listed, the minimum gate count and minimum depth may occur in different variants. ABC columns correspond only to the evaluated synt and transtoch flows shown here. The spacecraft-autonomy testcase is not included in this table because it is presently being retained as a GT input-loader regression/debug case rather than as a synthesis result.

FSM / memory-oriented PDBF synthesis results

These benchmarks provide direct ABC/GT comparison where an ABC result is available, together with multiple GT netlist variants when they were obtained.

The first line of each benchmark section identifies the benchmark and gives PI, PO, Cubes, the available ABC result, the first GT result, and the PLA download link. Additional lines show alternative GT netlist variants for the same PDBF.

Semantic PDBF synthesis results with available ABC comparisons

These semantic benchmarks provide direct ABC/GT comparison where an ABC result is available, together with multiple GT netlist variants when they were obtained.

The first line of each benchmark section identifies the benchmark and gives PI, PO, Cubes, the available ABC result, the first GT result, and the PLA download link. Additional lines show alternative GT netlist variants for the same PDBF.

Medium-input semantic PDBF benchmarks

In this benchmark suite, examples with hundreds to several thousand primary inputs are classified as medium-input PDBFs. The cases below model networking, security, storage, telecommunications and policy/control hardware.

The PLA files should be uploaded using exactly the benchmark filenames shown in the first column.

Contextual PDBF synthesis: blockwise and whole-design examples

These three examples compare contextual PDBF synthesis at the block and whole-design levels across arithmetic, sequential/control, and instruction-decoding structures. For each example, the component blocks are synthesized using their specified contextual care domains, and the complete design is shown both as a blockwise assembled implementation and as a directly synthesized whole contextual PDBF.

The Design column identifies the individual contextual block or the corresponding whole-design case. Where multiple ABC or GT synthesis variants are available, they are shown on additional lines for the same design.

“Whole — Assembled” denotes the complete function corresponding to the interconnected block implementation; “Whole — Contextual” denotes direct synthesis of the corresponding externally specified whole-design PDBF. Cube counts describe specified PLA care terms.

Randomly generated PDBFs: cube quantity to netlist parameters comparison

This experiment keeps the benchmark size fixed at 250 primary inputs and 1 primary output while increasing the number of PDBF cubes from 16 to 2,000. The table compares the resulting ABC and GT netlist gate counts and logic levels.

Each PLA button links to /benchmarks/<Benchmark>.pla.

PDBF input-scalability challenge

This separate series studies synthesis as the primary-input dimension grows from hundreds to tens of thousands, hundreds of thousands and one million inputs.

The results illustrate that primary-input count alone does not determine synthesis difficulty. The care structure, number of outputs, cube structure and interactions among conditions can be equally important.

Reported synthesis metrics

PI — number of primary inputs. PO — number of primary outputs. Cubes — number of PLA product terms.

For the GT results, Gates denotes the number of internal two-input simple/AIG logic nodes. Complemented AIG edges do not count as additional gates. Levels is the maximum logic depth from a primary input to a primary output.

GT Time is the reported synthesis runtime in seconds for the corresponding experiment.

Verification rules and acceptance criteria

A synthesized network is a valid implementation of a benchmark only if it satisfies every specified PDBF output value over the complete care domain of the PLA.

1. For every PLA cube and every output specified as 0, the synthesized output must be 0 for every concrete binary input assignment covered by that cube.
2. For every PLA cube and every output specified as 1, the synthesized output must be 1 for every concrete binary input assignment covered by that cube.
3. An output value - is unrestricted. A term for which all outputs are - imposes no PDBF constraint and should not be included in the effective truth table.
4. Verification must cover the complete input region represented by a cube, not only one representative minterm. If a PLA input is - and belongs to the effective support of the synthesized output, all relevant assignments of that free support variable must be checked or proven equivalent.
5. If all primary inputs in the effective support of an output are fixed within a PLA cube, evaluation of that support assignment proves the output over the complete cube; primary inputs outside the output support cannot affect the result.
6. Two overlapping cubes may not impose contradictory values on the same output. If two terms require opposite values, 0/1 or 1/0, for an output, their input cubes must be disjoint. Therefore at least one input position must contain an explicit complementary pair 0/1 or 1/0.
7. Behavior outside the PDBF care domain is unrestricted. Two valid synthesized networks do not have to be globally equivalent if they make different choices in don't-care regions.

Results obtained with other synthesis tools

We welcome independent experiments with these benchmarks. If you obtain a synthesis result using another combinational logic synthesis tool, please inform us of the result and the synthesis conditions.

For meaningful comparison, please identify the tool and version, synthesis commands/options, hardware platform, runtime, peak memory if available, gate/node count and logic depth. The resulting implementation can be validated against the original PLA using the verification criteria above.

A valid result with fewer gates, fewer levels, or competitive synthesis time is welcome.

Input-size terminology used in this suite

The terms below are benchmark-suite classifications rather than claims of universal EDA terminology: